The present invention relates to a display device, and more particularly, to an active matrix type display device thereof.
In an active matrix type liquid crystal display device, pixel regions are formed on a liquid crystal side surface of one of a pair of substrates, which are arranged so as to face each other in an opposed manner, with a liquid crystal being disposed therebetween. The pixels are formed as regions which are surrounded by gate signal lines that extend in the x direction and are arranged in parallel in the y direction and drain signal lines that extend in the y direction and are arranged in parallel in the x direction.
Each pixel region is provided with a thin film transistor, which is operated upon receiving a scanning signal from one gate signal line, and a pixel electrode to which video signals from the drain signal line are supplied through the thin film transistor.
This pixel electrode generates an electric field between the pixel electrode and a counter electrode which is formed on the other substrate side, for example, and the light transmittivity of the liquid crystal disposed between these electrodes is controlled by this electric field.
Such a liquid crystal display device is provided with a scanning signal driving circuit, which supplies scanning signals to respective gate signal lines and a video signal line driving circuit which supplies video signals to respective drain signal lines.
In view of the fact that the scanning signal driving circuit and the video signal line driving circuit are constituted of a large number of MIS (metal insulator semiconductor) transistors having a constitution similar to that of the thin film transistors formed inside of the pixel regions, a technique has been employed in which semiconductor layers of these respective transistors are formed of polycrystalline silicon (p-Si), and the scanning signal driving circuit and the video signal line driving circuit are formed on a surface of one substrate along with the formation of the pixels.
The scanning signal driving circuit is a circuit which mainly uses a shift register, and the video signal line driving circuit also uses a shift register at a portion thereof. However, there has been a recent demand for a shift register which can be operated at high speed at a low voltage and with a low power and has no through-current. To meet this demand, a shift register which is referred to as dynamic ratio shift register has been proposed, for example.
A dynamic ratio shift register of the type mentioned above has been disclosed in Japanese Patent Publication No. 45638/1987, for example, and the constitution thereof is illustrated in FIG. 9A. Further, FIG. 9B shows a timing chart of the circuit shown in FIG. 9A, which timing chart shows respective outputs VN1 and VN6 at nodes N1 and N6 corresponding to an input pulse "PHgr"IN and synchronous pulses "PHgr"1, "PHgr"2.
First of all, when the synchronous pulse "PHgr"1 is changed from a Low level (referred to as xe2x80x9cLxe2x80x9d hereinafter) to a High level (referred to as xe2x80x9cHxe2x80x9d hereinafter) at the time t1, the input pulse "PHgr"IN becomes xe2x80x9cHxe2x80x9d, and, hence, the potential VN1 of the node N1 is changed from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d through a NNT1.
Assuming xe2x80x9cLxe2x80x9d of the input pulse "PHgr"IN and the synchronous pulses "PHgr"1, "PHgr"2 having inverse phases from each other as a ground level (GND), and the xe2x80x9cHxe2x80x9d state of the input pulse "PHgr"IN and the synchronous pulses "PHgr"1, "PHgr"2 as a threshold value Vth of V"PHgr" less than NNT1, the potential VN1 at this point of time can be substantially expressed by the following equation (1). Here, V"PHgr" indicates the voltage at the xe2x80x9cHxe2x80x9d level of the synchronous pulses "PHgr"1, "PHgr"2 and NNT1 indicates a MOS transistor.
VN1=V"PHgr"xe2x88x92Vthxe2x80x83xe2x80x83(1)
Even when the synchronous pulse "PHgr"1 falls from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d at the time t2, the input pulse "PHgr"IN remains at xe2x80x9cHxe2x80x9d level, and, hence, the output VN1 holds the voltage expressed by the equation (1). In a strict sense, at a point of time at which the synchronous pulse "PHgr"1 falls, the potential becomes lower than the voltage expressed by the equation (1) due to a capacitive coupling between a gate of the transistor NNT1 and the node N1 or the like. However, such a phenomenon is not essential in the explanation of the operation, and, hence, the phenomenon is ignored. Since the NNT1 turns OFF, the node N1 becomes a floating node.
Subsequently, when the synchronous pulse "PHgr"2 is changed from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d at the time t2, provided that the following equation (2) is satisfied,
V"PHgr"xe2x88x92Vthxe2x89xa7V"PHgr"xe2x80x83xe2x80x83(2)
The MOS transistor NNT2 becomes the ON state and the pulse "PHgr"2 enters the node N2. At this point of time, due to the coupled capacitance Cb1, which is referred to as a bootstrap capacitance that is inserted between the nodes N1 and N2, a voltage rise on a point of the node N2 is transmitted to the node N1 which is in the floating state, so that the potential of the node N2 also rises.
Assume that the rising potential of the node N2 as xcex94VN2, the output VN1 is given by a following equation (3):
VN1=(V"PHgr"xe2x88x92Vth)+xcex94VN2 (Cb/Cb(Cb+Cs))xe2x80x83xe2x80x83(3)
Here, the capacitance Cb includes, besides the capacitance shown in the circuit diagram, such as the preceding coupled capacitance CB1, all of the coupled capacitance of synchronous pulse "PHgr"2 and the node N1, which include the capacitance generated by the gate, the drain and the source of the transistor NMT2, or an inversion layer (channel) formed below the gate, and further include the direct connection capacitance between the wiring of the synchronous pulse "PHgr"2 and the node N1. Further, Cs indicates a capacitance obtained by subtracting the above-mentioned bootstrap capacitance Cb from the whole capacitance of the node N1 and constitutes so-called parasitic capacitance.
Here, provided that a following equation ("PHgr"is satisfied at xcex94VN2V"PHgr".
(V"PHgr"xe2x88x92Vth)+V"PHgr"(Cb/Cb (Cb+Cs)) greater than V"PHgr"+Vthxe2x80x83xe2x80x83(4)
This implies that the gate voltage of the MOS transistor NMT2, that is, the output VN1, becomes higher than V"PHgr"+Vth. Accordingly, the output VN2 can be set to the potential of the voltage V"PHgr". By suitably selecting the capacitance Cb1, which constitutes a design element, it is easy to satisfy the above-mentioned equation (4), and, hence, the output VN2 can be set to the potential of the voltage V"PHgr".
Here, at the same time, the potential of the node N3 takes a value expressed by a following equation (5) through a MOS transistor NMT3, which is subjected to the diode connection.
VN3=V"PHgr"Vthxe2x80x83xe2x80x83(5)
Since the MOS transistor NMT3 is subjected to the diode connection, even when the synchronous pulse "PHgr"2 is changed from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d at the time t3, the state expressed by the above equation (5) can be held.
When the synchronous pulse "PHgr"1 is changed from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d at the time t3, an operation similar to that expressed by the equation (3) occurs at the node N3 and a MOS transistor NMT 5, so that the outputs VN3, VN4 respectively generate the change of potential as schematically shown in FIG. 1B.
Here, when the nodes N2, N4, N6 are used as output nodes, shift pulses (VN2, VN4, VN6) having the potential equal to that of xe2x80x9cHxe2x80x9d of the synchronous pulse can be obtained, and the dynamic operation which does not generate a through-current can be performed, as apparent from the above-mentioned operations.
However, when the dynamic ratio register having such a constitution is formed by directly providing MIS transistors having semiconductor layers which are made of polycrystalline silicon (p-Si) to surfaces of substrates (glass substrates) which are arranged to face each other in an opposed manner through a liquid crystal, it has been confirmed that the dynamic ratio register operates in an extremely unstable manner, so that the countermeasure to cope with such a phenomenon is needed.
That is, the capacitance, when the floating nodes, such as N1, N3, are at the xe2x80x9cLxe2x80x9d level, is extremely small, and the other capacitance of the nodes N1, N2, including Cdg1, Cdg2, is, as shown at Cdg1, Cgg2 of FIG. 9A, extremely small compared to the coupled capacitance between the synchronous pulse and the drain gates of the nodes Ni, N3. Hence, there exists a high possibility that unselected transistors also will be turned xe2x80x9cONxe2x80x9d. When the circuit remains as it is, the design and the operational voltage are considerably restricted for holding the xe2x80x9cOFFxe2x80x9d state.
With respect to the monocrystalline semiconductor at the dynamic ratioless shift register which are made of thin film transistors formed on the glass substrate, the main reasons why the capacitance becomes very small when the floating node is at the xe2x80x9cLxe2x80x9d level are as follows.
FIG. 10A is a cross-sectional schematic view of an n-type MOS transistor formed on a monocrystalline semiconductor. A semiconductor integrated circuit having a substrate which constitutes the semiconductor is generally used in a form in which it is biased (including the case that it is grounded) for element separation or the like.
Accordingly, as shown in FIG. 10A, through a depletion layer capacitance Csw due to an inverse bias between a source (a diffusion layer) and a well (or a substrate), a depletion layer capacitance Cdw between a drain and the well and a capacitance Cgw between a gate and the well, the source, the drain and the gate are capacitively coupled with the well. Further, the wiring is also capacitively coupled with the substrate or the well which is disposed immediately below the winding with the capacitance Clw through a thick insulation film. These capacitance belong to a group of capacitances which are usually called parasitic capacitance.
Accordingly, at a portion of the node N3 shown in FIG. 9A, a large coupling capacitance with the well can be obtained due to the capacitance Csw of the NMT3 (Csw3), the capacitance Cgw of the NMT6 (Cgw6), the capacitance Cdw (Cdw6), the capacitance Csw of the NMT7 (Csw7) and the capacitance Clw (Clw3) of the wiring which constitutes this node.
Further, by making the bootstrap capacitance have the enhanced MOS capacitive constitution which is shown in FIG. 10B and FIG. 10C, the well is capacitively coupled with an inversion layer that extends from a depletion layer which constitutes a separate node at the xe2x80x9cONxe2x80x9d time, as shown in FIG. 10B so that an efficient bootstrap effect (a boosting effect) is obtained, while a coupled capacitance Cb1(w) with the well is obtained at the xe2x80x9cOFFxe2x80x9d time, as shown in FIG. 10B.
Accordingly, when the node N3 is at the xe2x80x9cLxe2x80x9d level, even when the node N3 is floating on the circuit shown in FIG. 9A, the large capacitance can be ensured with the bias of the well through the above-mentioned coupled capacitance. With respect to the capacitance, the sum of Cdw of the NMT3 (Cdw1) and the space capacitance C1"PHgr"1 between the wiring of "PHgr"1 and the node N3 is sufficiently small, and hence, the potential difference xcex94VN3 of the node N3 when the wiring "PHgr"1 is changed from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d is substantially expressed by a following equation (6).
xcex94VN3=V"PHgr"xc3x97(Cdw+C1"PHgr"1)/(Cdw1|C1"PHgr"2+Csw3+Cgw6+Cdw6+Csw7+Cb1(w))xe2x80x83xe2x80x83(6)
Further, as explained above, since the relationship expressed by the following equation (7) is established,
Cdw1+C1"PHgr"2 less than  less than Csw3+Cgw6+Cdw6+Csw7+Cb1(w)xe2x80x83xe2x80x83(7)
it becomes easy to satisfy a following equation (8).
xcex94VN3 less than Vthxe2x80x83xe2x80x83(8)
However, when a similar circuit made of monocrystalline thin film transistors is formed on a glass substrate, the above-mentioned operation is not achieved.
FIG. 10D is a cross-sectional schematic view of the monocrystalline thin film transistor which is formed on the glass substrate. Provided that the substrate is formed of an insulating body, once a p layer arranged below a source, a drain or a gate becomes floating, the capacitance which can be coupled becomes the depletion layer capacitance Cdp, Csp between the source, or drain or the gate and the p layer arranged below the source, the drain or the gate or the small space capacitance Cs1, Cp1, Cd1 between the player and the wiring which is disposed so as to be remote from the source, drain or the gate. To take a portion of the node N3 of the circuit shown in FIG. 9A as an example, in the same manner as the above-mentioned example, the node N3 is capacitively coupled with the node N2 through the source Csp3 of the MOS transistor NNT3. Since the node N2 is also floating, the path is divided into a path which brings about the capacitive coupling with the node N1 through the capacitance Cb1 and a path which brings about the capacitive coupling with the synchronous pulse "PHgr"2 through the SP2 of the MOS transistor NMT2. Since the node N1 is also floating, the path is divided into a path which brings about the capacitive coupling with the input pulse "PHgr"IN through the capacitance Csp1 of the MOS transistor NMT1 and a path which brings about the capacitive coupling with the ground potential Vss through the capacitance Csp4 of the MOS transistor NMT4, which brings about the capacitive coupling with the synchronous pulse "PHgr"1 through the capacitance Csg1 of the MOS transistor NMT1.
That is, both capacitance also become very small and the coupling with the synchronous pulse "PHgr"1 functions in such a manner that the output VN3 is boosted when the synchronous pulse "PHgr"1 becomes xe2x80x9cLxe2x80x9dxe2x80x9cHxe2x80x9d.
Although the source of a MOS transistor NMT7 is capacitively coupled with the ground potential VSS through the capacitance Csp7, this is also not significant. Further, the node N3 is capacitively coupled with the node N4 through the capacitance Cb2 so that the node N4 is also floating. The wiring which constitutes the node N3 does not have the capacitance immediately below the node N3, and the node N3 has only a weak capacitive coupling with any one the of wirings through the space capacitance.
The node N3 is capacitively coupled with the synchrous pulse "PHgr"1 through the capacitance Cdg5 of the MOS transistor NMT5. This capacitive coupling is the direct capacitive coupling with the outside and is relatively large. This capacitance becomes a cause of instability.
Assuming the total sum of the above-mentioned other secondary coupled capacitance of the node N3, except for the capacitance Cdg5 as the capacitance CN3, the change of potential xcex94WN3 of the node N3 when the synchronous pulse "PHgr"1 is changed from xe2x80x9cLxe2x80x9dxe2x80x9cHxe2x80x9d is substantially expressed by a following equation (9). Since the capacitance CN3 is not so large as mentioned above, depending on values of the voltage V"PHgr" and the capacitance Cdg5 (W size design of the MOS transistor NMT5 or the wiring layout of the synchronous pulse "PHgr"1), conditions shown by the following equation (10) are easily brought about.
xcex94VN3=V"PHgr"xc3x97(Cdg5/(CdgS+CN3))xe2x80x83xe2x80x83(9)
xcex94VN3xe2x89xa7Vthxe2x80x83xe2x80x83(10)
Once the conditions indicated by the above equation (10) are satisfied, the capacitance Cgp of the MOS transistor NMT5 (the capacitance with the inversion layer) and the bootstrap capacitance Cb2 are changed to the coupled capacitance with the node N3 and the "PHgr"1 in an opposed manner, so that the possibility that the MOS transistor NMT3 turns completely xe2x80x9cONxe2x80x9d due to the bootstrap effect is extremely increased. That is, an unstable operation is generated such that nodes which are irrelevant to the node under control become xe2x80x9cHxe2x80x9d and generate outputs or start the scanning from such portions.
The present invention has been made in view of such a circumstance, and it is an object of the present invention to provide a display device having a dynamic ratioless shift register which ensures stable operation and which can increase the degree of freedom of design.
A summary of typical features and aspects of the invention disclosed in the present application are as follows.
Aspect 1.
The display device according to the present invention is, for example, characterized in that the display device is provided with a driving circuit which includes a shift register on a surface of a substrate, and the shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. The first terminal of the first MISTFT is connected to receive an input pulse, and a gate terminal of the first MISTFT is connected to receive a first synchronous pulse, thus forming an inputting part. The second terminal of the first MISTFT is connected to a gate terminal of the second MISTFT and the first terminal of the fourth MISTFT, and, further, it is connected to the first terminal of the first capacitance element. The second terminal of the first capacitance is connected to a fixed voltage and the first terminal of the second MISTFT is connected to receive a second synchronous pulse which has an inverse phase with respect to the first synchronous pulse. The second terminal of the second MISTFT is connected to the first terminal and a gate terminal of the third MISTFT, and it is further connected to the first terminal of the second capacitance. The second terminal of the second capacitance is connected to the second terminal of the first MISTFT, the gate terminal of the second MISTFT and the first terminal of the fourth MISTFT. The second terminal of the third MISTFT is connected to a gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT, and it is further connected to the first terminal of the third capacitance element, thus forming a first output terminal. The second terminal of the third capacitance is connected to receive a fixed voltage and the first terminal of the fifth MISTFT is connected to the first synchronous pulse. The second terminal of the fifth MISTFT is connected to the first terminal and a gate terminal of the sixth MISTFT and a gate terminal of the fourth MISTFT, and it is further connected to the first terminal of the fourth capacitance to form the second output terminal. The second terminal of the fourth capacitance is connected to the second terminal of the third MISTFT, the gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT. The second terminal of the fourth MISTFT and the second terminal of the seventh MISTFT are connected to a fixed power source or a ground potential which is equal to the voltage which will be the source voltage of the MISTFT which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT, wherein a pulse which is shifted by one clock and corresponds to a pulse inputted to the gate terminal of the fourth MISTFT is inputted to the gate terminal of the seventh MISTFT.
In the display device having such a constitution as described above, one side of the load capacitance is connected to a node which can be floating and the other end side of the load capacitance is connected to the fixed potential or the like. Accordingly, the design tolerance in the state that the above-mentioned unstable elements are eliminated can be broadened so that a stable dynamic ratioless shift register including thin film transistors made of polycrystalline silicon can be realized.
Aspect 2.
The display device according to the present invention is characterized in that, for example, on the premise of the constitution of the aspect 1, n basic circuits, each of which is constituted of the second to seventh MISTFTs and first to fourth capacitance are connected in multi-stages. The gate terminal of the MISTFT which corresponds to the second MISTFT of the ith basic circuit is connected to the second terminal of the MISTFT corresponding to the sixth MISTFT of the (ixe2x88x921)th basic circuit. The gate terminal of the MISTFT which corresponds to the seventh MISTFT of the ith basic circuit is connected to the second terminal of the MISTFT corresponding to the second MISTFT of the (i+1)th basic circuit. The pulse which corresponds to the pulse inputted to the gate terminal of the fourth MISTFT of the basic circuit of a next stage and is shifted by one clock is inputted to the gate terminal of the MISTFT which corresponds to the seventh MISTFT of the nth basic circuit.
Aspect 3.
The display device according to the present invention is characterized in that, for example, on the premise of the constitution of the aspect 2, the second MISTFT is incorporated into the first basic circuit, and the first MISTFT and the second MISTFT are incorporated into each one of the second and succeeding basic circuits. The first MISTFT has the gate terminal thereof connected to the input terminal for receipt of the input pulse, the first terminal thereof connected to the gate terminal of the MISTFT corresponding to the second MISTFT, and the second terminal thereof connected to a fixed power source or a ground potential which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses, which is not less than the threshold voltage of the fourth MISTFT. The second MISTFT has the gate terminal thereof connected to the input terminal of the input pulse, the first terminal thereof connected to the gate terminal the fifth MISTFT or the gate terminal of a MISTFT corresponding to the fifth MISTFT, and the second terminal thereof connected to a fixed power source or a ground potential, which is equal to a voltage which becomes a source voltage of the MISTFT out of the voltages of the first and second synchronous pulses, or which is not different from the voltage which becomes the source voltage of the first or second synchronous pulse to an extent that the fixed power source or the ground potential at least does not exceed a threshold value voltage of the fourth MISTFT.
Aspect 4.
The display device according to the present invention is, for example, characterized in that the display device is provided with a driving circuit which includes a shift register on a surface of a substrate, and the shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. The first terminal and a gate terminal of the first MISTFT are connected to receive an input pulse, thus forming an inputting part. The second terminal of the first MISTFT is connected to a gate terminal of the second MISTFT and the first terminal of the fourth MISTFT, and, further it is connected to a first terminal of a first capacitance element. The second terminal of the first capacitance element is connected to a fixed voltage and the first terminal of the second MISTFT is connected to receive a second synchronous pulse which has an inverse phase with respect to the first synchronous pulse. The second terminal of the second MISTFT is connected to the first terminal and a gate terminal of the third MISTFT, and is it further connected to a first terminal of a second capacitance. The second terminal of the second capacitance is connected to the second terminal of the first MISTFT, the gate terminal of the second MISTFT and the first terminal of the fourth MISTFT. The second terminal of the third MISTFT is connected to a gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT, and it is further connected to the first terminal of the third capacitance element, thus forming a first output terminal. The second terminal of the third capacitance is connected to a fixed voltage and the first terminal of the fifth MISTFT is connected to the first synchronous pulse. The second terminal of the fifth MISTFT is connected to the first terminal and a gate terminal of the sixth MISTFT and a gate terminal of the fourth MISTFT, and it is further connected to the first terminal of the fourth capacitance to form the second output terminal. The second terminal of the fourth capacitance is connected to the second terminal of the third MISTFT, the gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT. The second terminal of the fourth MISTFT and the second terminal of the seventh MISTFT are connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT, wherein a pulse which is shifted by one clock and corresponds to a pulse inputted to the gate terminal of the fourth MISTFT is inputted to the gate terminal of the seventh MISTFT.
Aspect 5.
The display device according to the present invention is characterized in that, for example, on the premise of the constitution of the aspect 4, n basic circuits, each of which is constituted of the second to seventh MISTFT5 and first to fourth capacitance, are connected in multi-stages. The gate terminal of the MISTFT, which corresponds to the second MISTFT of the ith basic circuit, is connected to the second terminal of the MISTFT corresponding to the sixth MISTFT of the (ixe2x88x921)th basic circuit. The gate terminal of the MISTFT, which corresponds to the seventh MISTFT of the ith basic circuit, is connected to the second terminal of the MISTFT corresponding to the second MISTFT of the (i+1)th basic circuit. The pulse which corresponds to the pulse inputted to the gate terminal of the fourth MISTFT of the basic circuit of a next stage and is shifted by one clock is inputted to the gate terminal of the MISTFT which corresponds to the seventh MISTFT of the nth basic circuit.
Aspect 6.
The display device according to the present invention is characterized in that, for example, on the premise of the aspect 5, the second MISTFT is incorporated into the first basic circuit, and the first MISTFT and the second MISTFT are incorporated into each one of the second and succeeding basic circuits. The first MISTFT has the gate terminal thereof connected to the input terminal of the input pulse, the first terminal thereof connected to the gate terminal of the MISTFT corresponding to the second MISTFT, and the second terminal thereof connected to a fixed power source or a ground potential which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT. The second MISTFT has the gate terminal thereof connected to the input terminal of the input pulse, the first terminal thereof connected to the gate terminal of the fifth MISTFT or the gate terminal of a MISTFT corresponding to the fifth MISTFT, and the second terminal thereof connected to a fixed power source or a ground potential which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT.
Aspect 7.
The display device according to the present invention is, for example, characterized in that the display device is provided with a driving circuit which includes a shift register on a surface of a substrate, and the shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. The first terminal and a gate terminal of the first MISTFT are connected to an input pulse thus forming an inputting part. The second terminal of the first MISTFT is connected to a gate terminal of the second MISTFT and the first terminal of the fourth MISTFT, and, further, it is connected to a fixed voltage through the first capacitance. The first terminal of the second MISTFT is connected to the second synchronous pulse which has an inverse phase with respect to the first synchronous pulse. The second terminal of the second MISTFT is connected to the first terminal and a gate terminal of the third MISTFT, and it is further connected to the second terminal of the first MISTFT, the gate terminal of the second MISTFT and the first terminal of the fourth MISTFT. The second terminal of the third MISTFT is connected to a gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT, and it is further connected to the fixed voltage through the third capacitance element. The first terminal of the fifth MISTFT is connected to the first synchronous pulse. The first terminal of the fifth MISTFT is connected to the first terminal and a gate terminal of the sixth MISTFT and a gate terminal of the fourth MISTFT, and it is further connected to the second terminal of third MISTFT, the gate terminal of the fifth MISTFT and the first terminal of the seventh MISTFT through the fourth capacitance element. The second terminal of the fourth MISTFT is connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT, wherein a pulse which is shifted by one clock and corresponds to a pulse inputted to the gate terminal of the fourth MISTFT is inputted to the gate terminal of the seventh MISTFT.
Aspect 8.
The display device according to the present invention is characterized in that, for example, on the premise of the constitution of the aspect 7, n basic circuits, each of which is constituted of the second to eleventh MISTFT5 and the first and second capacitance are connected in multi-stages. The gate terminal of the MISTFT, which corresponds to the second MISTFT of the ith basic circuit, is connected to the second terminal of the MISTFT corresponding to the tenth MISTFT of the (ixe2x88x921)th basic circuit. The gate terminal of the MISTFT which corresponds to the eighth MISTFT and the first terminal of the MISTFT which corresponds to the seventh MISTFT of the ith basic circuit are connected to the second terminal of the MISTFT corresponding to the sixth MISTFT of the (i+1)th basic circuit. The pulse which corresponds to the pulse inputted to the gate terminal of the fourth MISTFT and is shifted by one clock is inputted to the gate terminal of the MISTFT which corresponds to the eighth MISTFT and the first terminal of the MISTFT which corresponds to the seventh MISTFT of the nth basic circuit.
Aspect 9.
The display device according to the present invention is, for example, characterized in that the display device is provided with a driving circuit which includes a shift register on a surface of a substrate, and the shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. The first terminal of the first MISTFT is connected to an input pulse, and a gate terminal of the first MISTFT is connected to the first synchronous pulse, thus forming an inputting part. The second terminal of the first MISTFT is connected a gate terminal of the fourth MISTFT and the first terminal of the third MISTFT, and, further, it is connected to the first terminal of the first capacitance. The second terminal of the first capacitance is connected to the second terminal of the fourth MISTFT, the first terminal and a gate terminal of the fifth MISTFT and the first terminal and a gate terminal of the sixth MISTFT, and it is further connected to a gate terminal of the seventh MISTFT, a gate terminal of the second MISTFT is connected to the input pulse, and the first terminal of the second MISTFT is connected to the second terminal of the eleventh MISTFT and a gate terminal of the third MISTFT. The second terminal of the second MISTFT and the second terminal of the seventh MISTFT are connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT. The second terminal of the third MISTFT is connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT. The first terminal of the fourth MISTFT is connected to the second synchronous pulse, and the second terminal of the fifth MISTFT is connected to a gate terminal of the ninth MISTFT and the first terminal of the eighth MISTFT. The second terminal of the second capacitance is connected to the second terminal of the ninth MISTFT, the first terminal and a gate terminal of the tenth MISTFT and the first terminal and a gate terminal of the eleventh MISTFT, and, further it is connected to the first terminal of the second capacitance element, thus forming the first output terminal. The first terminal of the seventh MISTFT is connected to the gate terminal of the eighth MISTFT, and the second terminal of the eighth MISTFT is connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT. The first terminal of the ninth MISTFT is connected to the first synchronous pulse, wherein a pulse which is shifted by one clock and corresponds to a pulse inputted to the gate terminal of the fourth MISTFT is inputted to the gate terminal of the eighth MISTFT and the first terminal of the seventh MISTFT.
Aspect 10.
The display device according to the present invention is characterized that, for example, on the premise of the constitution of the aspect 9, n basic circuits, each of which is constituted of the second, third, fourth, fifth, seventh, eighth, ninth and tenth MISTFTs and the first and second capacitance, are connected in multi-stages. The second terminal of a MISTFT which corresponds to the tenth MISTFT of the ith basic circuit is connected to the gate terminal of the MISTFT corresponding to the fourth MISTFT of the (ixe2x88x92i)th basic circuit. The second terminal of the MISTFT which corresponds to the seventh MISTFT and the gate terminal of the MISTFT which corresponds to the third MISTFT of the ith basic circuit are connected to the capacitance corresponding to the first capacitance of the (i+i)th basic circuit through the sixth MISTFT. The second terminal of the sixth MISTFT is connected to the second terminal of the MISTFT and the gate terminal of the MISTFT which corresponds to the third MISTFT and the first terminal and the gate terminal of the sixth MISTFT is connected to the capacitance.
Aspect 11.
The display device according to the present invention is characterized in that, for example, at respective basic circuits starting from a second basic circuit, the second terminal of first MISTFT, which has the first terminal thereof and a gate terminal thereof connected to an input pulse, is connected to the second terminal of a MISTFT which corresponds to an eleventh MISTFT. At respective basic circuits starting from a third basic circuit, the second terminal of the second MISTFT, which has the first terminal thereof and a gate terminal thereof connected to an input pulse, is connected to a gate terminal of a MISTFT which corresponds to the eighth MISTFT of the basic circuit, which forms a pre-stage of the subject basic circuit, and is connected to the second terminal of capacitance which corresponds to the first capacitance through the MISTFT. The second terminal of the MISTFT is connected to the second terminal of the second MISTFT, and the first terminal and the gate terminal are connected to the capacitance.
Aspect 12.
The display device according to the present invention is, for example, characterized in that the display device is provided with a driving circuit, which includes a shift register on a surface of a substrate, and the shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. The first terminal and a gate terminal of the first MISTFT are connected to receive an input pulse, thus forming an input part. The second terminal of the first MISTFT is connected to a gate terminal of the fourth MISTFT and the first terminal of the third MISTFT, and, further it is connected to the first terminal of the first capacitance. The second terminal of the first capacitance is connected to the second terminal of the fourth MISTFT, the first terminal and a gate terminal of the fifth MISTFT and the first terminal and a gate terminal of the sixth MISTFT, and it is further connected to a gate terminal of the seventh MISTFT. A gate terminal of the second MISTFT is connected to the input pulse, and the first terminal of the second MISTFT is connected to the second terminal of the eleventh MISTFT and a gate terminal of the third MISTFT. The second terminal of the second MISTFT and the second terminal of the seventh MISTFT are connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT. The second terminal of the third MISTFT is connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses which is not less than the threshold voltage of the fourth MISTFT.
The first terminal of the fourth MISTFT is connected to the second synchronous pulse, and the second terminal of the fifth MISTFT is connected to a gate terminal of the ninth MISTFT and the first terminal of the eighth MISTFT. The second terminal of the second capacitance is connected to the second terminal of the ninth MISTFT, the first terminal and a gate terminal of the tenth MISTFT and the first terminal and a gate terminal of the eleventh MISTFT, and, further it is connected to the first terminal of the second capacitance element thus, forming the first output terminal. The first terminal of the seventh MISTFT is connected to the gate terminal of the eighth MISTFT, and the second terminal of the eighth MISTFT is connected to a fixed power source or a ground potential, which is equal to the voltage which will be the source voltage of the MISTFT, which is included among the voltages of the first and second synchronous pulses, or which will be the source voltage of first and second synchronous pulses, which is not less than the threshold voltage of the fourth MISTFT. The first terminal of the ninth MISTFT is connected to the first synchronous pulse, wherein a pulse which is shifted by one clock and corresponds to a pulse inputted into the gate terminal of the fourth MISTFT is inputted to the gate terminal of the eighth MISTFT and the first terminal of the seventh MISTFT.
Aspect 13.
The display device according to the present invention is characterized in that, for example, on the premise of the constitution of the aspect 12, n basic circuits, each of which is constituted of the second, third, fourth, fifth, seventh, eighth, ninth and tenth MISTFTs and the first and second capacitance are connected in multi-stages. The second terminal of the MISTFT, which corresponds to the tenth MISTFT of the ith basic circuit, is connected to the gate terminal of the MISTFT corresponding to the fourth MISTFT of the (ixe2x88x921)th basic circuit. The second terminal of the MISTFT which corresponds to the seventh MISTFT and the gate terminal of the MISTFT which corresponds to the third MISTFT of the ith basic circuit are connected to the capacitance corresponding to the first capacitance of the (i+1)th basic circuit through the sixth MISTFT. The second terminal of the sixth MISTFT is connected to the second terminal of the MISTFT and the gate terminal of the MISTFT which corresponds to the third MISTFT and the first terminal and the gate terminal of the sixth MISTFT are connected to the capacitance.
Aspect 14.
The display device according to the present invention is characterized in that, on the premise of the aspect 13, at respective basic circuits starting from the second basic circuit, the second terminal of the first MISTFT, which has the first terminal thereof and a gate terminal thereof connected to an input pulse, is connected to the second terminal of a MISTFT which corresponds to the eleventh MISTFT. At respective basic circuits starting from the third basic circuit, the second terminal of the second MISTFT, which has the first terminal thereof and a gate terminal thereof connected to an input pulse, is connected to a gate terminal of a MISTFT which corresponds to the eighth MISTFT of a basic circuit, which forms a pre-stage of the subject basic circuit, and is connected to the second terminal of capacitance which corresponds to the first capacitance through the MISTFT. The second terminal of the MISTFT is connected to the second terminal of the second MISTFT and the first terminal and the gate terminal are connected to the capacitance.
Aspect 15.
The display device according to the present invention is, for example, provided with a ratioless dynamic shift"" register which includes multi-staged inverters on a substrate surface. The ratioless dynamic shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. Separate MISTFTs are connected in parallel to MISTFTs which are connected to ground levels of outputs of respective stages, and the separate MISTFTs are constituted such that each output is dropped to a ground level during a period other than a period in which a signal of High level is transmitted as an input signal of an inverter at a stage preceding to a stage which is constituted of the MISTFTs.
Aspect 16.
The display device according to the present invention is, on the premise of the constitution of the aspect 15, characterized in that the separate MISTFTs are operated by inputting outputs of the next stage, and each output is dropped to the ground level during the period other than the period in which the signal of High level is transmitted as the input signal of the inverter at the stage preceding to the stage which is constituted of the MISTFT.
Aspect 17.
The display device according to the present invention is, for example, on the premise of the constitution of the Aspect 15, characterized in that the separate MISTFT is operated by inputting a clock pulse, and each output is dropped to the ground level during the period other than the period in which the signal of High level is transmitted as the input signal of the inverter at the stage preceding to the stage which is constituted of the MISTFT.
Aspect 18.
The display device according to the present invention is, for example, characterized in that the display device is provided with a display driving circuit including a ratioless dynamic shift register which is comprised of multi-staged inverters on a substrate surface. The ratioless dynamic shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer, and the first MISTFT, and the second MISTFT which are connected in parallel to each other, are provided as MISTFTs which are connected to the ground levels of respective outputs of respective stages. Either one of the first MISTFT and the second MISTFT is constituted such that each output is dropped to the ground level during the period other than the period in which the signal of High level is transmitted as the input signal of the inverter at the stage preceding to the stage which is constituted of the MISTFT. A diode which constitutes the third MISTFT is provided between a gate of either one of the first MISTFT and the second MISTFT and a node to which a clock is supplied through a diode, such that a charge which is charged to the gate is prevented from the leakage to the node as an inverse current flow of the diode which is caused by the lowering of the potential of the node below the ground level.
Aspect 19.
The display device according to the present invention is, for example, characterized in that the display device is provided with a display driving circuit including a ratioless dynamic shift register which is comprised of multi-staged inverters on a substrate surface. The ratioless dynamic shift register is constituted of MISTFT5 which use polycrystalline silicon as a semiconductor layer, and a first MISTFT and a second MISTFT are provided, which drop respective outputs of respective stages to a ground level when the first clock and the second clock are in the xe2x80x9cONxe2x80x9d state and the third MISTFT and the fourth MISTFT which become the xe2x80x9cONxe2x80x9d state when the outputs are at the xe2x80x9cHighxe2x80x9d level and turn off the first MISTFT and the second MISTFT.
Aspect 20.
The display device according to the present invention is, for example, on the premise of the constitution of the Aspect 19, characterized in that the first clock is inputted to the gate of the first MISTFT through the first capacitance element, the second clock is inputted to the gate of the second MISTFT through the second capacitance element, and the fifth MISTFT and the sixth MISTFT which are respectively subjected to the diode connection are provided between the gate of the first MISTFT and the ground level and between the gate of the second MISTFT and the ground level.
Aspect 21.
The display device according to the present invention is, for example, characterized in that the display device is provided with a display driving circuit including a ratioless dynamic shift register which is comprised of multi-staged inverters on a substrate surface. The ratioless dynamic shift register is constituted of MISTFTs which use polycrystalline silicon as a semiconductor layer. A first MISTFT is provided, which is connected to ground levels of respective outputs of respective stages, and a second MISFT is provided, which is operated with an output of a preceding stage and has one end thereof connected to a ground level and the other end thereof connected to a clock through the first capacitance element and further has the other end thereof connected to a gate of the first MISTFT. A second capacitance element is disposed between the other end of the second MISTFT and the ground level.
Aspect 22.
The display device according to the present invention is, for example, on the premise of the Aspect 21, characterized in that the second capacitance element has a capacitance larger than a gate-drain capacitance of the second MISTFT.